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NJU6636
PRELIMINARY
16-CHARACTER 2-LINE DOT MATRIX LCD CONTROLLER DRIVER with Icon Display
! GENERAL DESCRIPTION
The NJU6636 is a Dot Matrix LCD controller driver for 16-character 2-line display with icon display in single chip. It contains voltage converter and regulator, bleeder resistor, CR oscillator, microprocessor Interface circuits, Instruction decoder controller, character generator ROM/RAM and common and segment drivers. The external power supply circuit is simplified by using the bleeder resistance to generate the bias level of LCD driving voltage internally. The microprocessor Interface circuits which operate 2MHz frequency, can be connected directly to serial or 8bit microprocessor. The character generator consists of 9,600 bits ROM and 64 x 5 bits RAM. The standard version ROM is coded with 240 characters including capital and small letter fonts. The 17-common (16 for character, 2 for icon) and 80-segment drive up to 16-character 2-line with 80 Icon LCD panel which divided two common electrode blocks.
! PACKAGE OUTLINE
NJU6636CJ
! FEATURES
# # # # # # # # # # # # # # # 16-character 2-line Dot Matrix LCD Controller Driver Maximum 80 Icon Display Serial, 8 Bi t Microprocessor direct Interface Display Data RAM :32 x 8 bits : Maximum 16-character 2line Display Character Generator ROM :9,600 bits ; 240 characters for 5 x 8 dots Character Generator RAM :64 x 5 bits ; 8 Patterns( 5 x 8 dots) Icon Display RAM :16 x 5 bits ; Maximum 80 icon Microprocessor direst accessing to Display Data RAM and Character Generator RAM High Voltage LCD Driver :17-common / 80-segment Duty Ratio :1/9, 1/17 Duty ( Programmable ) and 1/5 bias Useful Instruction Set :Clear Display, Returns Home, Display ON/OFF Cont, Cursor ON/OFF Cont, Display Blink, Cursor Shift, Character Shift Power On Reset / Hardware Reset Function Voltage regulator on chip ( software contrast control : 8 Step ) Oscillation Circuit on chip Bleeder Resistor on chip ( Mask Option ) Version Bleeder Resistor(V0 to VSS) NJU6636A 40k (Typ.) : 1/5 Bias NJU6636B 20k (Typ.) : 1/5 Bias Low Power Consumption ( Power down function ) Common and Segment driver Location order Select Function ( SEL1 & SEL2 Terminal ) Operating Voltage --- +2.4 to 5.5V ( Except LCD Driving Voltage ) LCD Driving Voltage --- 6.0V Max. Package Outline --- Bumped Chip C-MOS Technology ( P-sub )
# # # # # #
Ver.2004-08-06
-1-
NJU6636
! PAD LOCATION
Mode A (TOP VIEW) SEL1=0, SEL2=0
DUMMY9 COM9 DUMMY7 DUMMY12 COM16 COMMK2 DUMMY10
DUMMY13 DUMMY15 SEG80
85
69
DUMMY6 DUMMY3 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 E R/W RS RESb VDDA P/S VSSA SEL2 VDDA SEL1 VSSA REGON VDDA DNC OSC1 VSS VSS VSS VSS VOUT VOUT VOUT VSS VSS VSS VSS C1+ C1+ C1+ C1C1C1VREG VREG VREG VSS VSS VSS VSS VCI VCI VCI VCI V0 V0 V0 V2 V2 V3 V3 DUMMY2
Alignment Mark Alignment mark coordinates A
Y
B A
X
B A : 25um B : 50um Alignment mark coordinates ( -2495, 878) ( 2495, -878)
Chip Size : 5.33 x 2.08mm Chip Center : X=0m, Y=0m Bump Size : 35 x 104m Bump Height : 17.5um (Typ.) Bump Material : Au
SEG1 DUMMY16 DUMMY18
170
185
1
DUMMY0
COM8 DUMMY21
DUMMY22 COMK1 COM1
DUMMY24
Note) A mode setup is decided by the combination of SEL1 and SEL2 terminals.
DUMMY19
-2-
Ver.2004-08-06
NJU6636
Mode B (TOP VIEW) SEL1=1, SEL2=1
DUMMY12 DUMMY7 COM1 COMMK1 DUMMY10 DUMMY9 COM8
DUMMY13 DUMMY15 SEG1
85
69
DUMMY6 DUMMY3
Y
X
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 E R/W RS RESb VDDA P/S VSSA SEL2 VDDA SEL1 VSSA REGON VDDA DNC OSC1 VSS VSS VSS VSS VOUT VOUT VOUT VSS VSS VSS VSS C1+ C1+ C1+ C1C1C1VREG VREG VREG VSS VSS VSS VSS VCI VCI VCI VCI V0 V0 V0 V2 V2 V3 V3 DUMMY2
SEG80 DUMMY16 DUMMY18
170
185
1
DUMMY0
COM9 DUMMY21
DUMMY22 COMK2 COM16
DUMMY24
Note) A mode setup is decided by the combination of SEL1 and SEL2 terminals
DUMMY19
Ver.2004-08-06
-3-
NJU6636
Mode C (TOP VIEW) SEL1=1, SEL2=0
DUMMY12 COM1 COMMK1 DUMMY10 DUMMY9 COM8 DUMMY7
DUMMY13 DUMMY15 SEG80
85
69
DUMMY6 DUMMY3
Y
X
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 E R/W RS RESb VDDA P/S VSSA SEL2 VDDA SEL1 VSSA REGON VDDA DNC OSC1 VSS VSS VSS VSS VOUT VOUT VOUT VSS VSS VSS VSS C1+ C1+ C1+ C1C1C1VREG VREG VREG VSS VSS VSS VSS VCI VCI VCI VCI V0 V0 V0 V2 V2 V3 V3 DUMMY2
SEG1 DUMMY16 DUMMY18
170
185
1
DUMMY0
COM9 DUMMY21
DUMMY22 COMMK2 COM16
DUMMY24
Note) A mode setup is decided by the combination of SEL1 and SEL2 terminals
DUMMY19
-4-
Ver.2004-08-06
NJU6636
Mode D(TOP VIEW) SEL1=0, SEL2=1
COM16 COMMK2 DUMMY10 DUMMY12 DUMMY9 COM9 DUMMY7
DUMMY13 DUMMY15 SEG1
85
69
DUMMY6 DUMMY3
Y
X
DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 E R/W RS RESb VDDA P/S VSSA SEL2 VDDA SEL1 VSSA REGON VDDA DNC OSC1 VSS VSS VSS VSS VOUT VOUT VOUT VSS VSS VSS VSS C1+ C1+ C1+ C1C1C1VREG VREG VREG VSS VSS VSS VSS VCI VCI VCI VCI V0 V0 V0 V2 V2 V3 V3 DUMMY2
SEG80 DUMMY16 DUMMY18
170
185
1
DUMMY0
COM8 DUMMY21
DUMMY22 COMMK1 COM1
DUMMY24
Note) A mode setup is decided by the combination of SEL1 and SEL2 terminals
DUMMY19
Ver.2004-08-06
-5-
NJU6636
! PAD COORDINATES 1
PAD No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Terminal
DUMMY0 DUMMY1 DUMMY2 V3 V3 V2 V2 V0 V0 V0 VCI VCI VCI VCI VSS VSS VSS VSS VREG VREG VREG C1C1C1C1+ C1+ C1+ VSS VSS VSS VSS VOUT VOUT VOUT VDD VDD VDD VDD VSS VSS VSS VSS OSC1 DNC VDDA REGON VSSA SEL1 VDDA SEL2
X= m
-2503 -2448 -2393 -2283 -2228 -2063 -2008 -1953 -1898 -1843 -1788 -1733 -1678 -1623 -1568 -1513 -1458 -1403 -1348 -1293 -1238 -1183 -1128 -1073 -963 -908 -853 -798 -743 -688 -633 -578 -523 -468 -413 -358 -303 -248 -193 -138 -83 -28 28 138 248 303 413 468 578 633
Y= m
-891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891
PAD No.
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Chip Size(5330m X 2080m) Terminal X= m Y= m
VSSA PS VDDA RESb RS RW E DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DUMMY3 DUMMY4 DUMMY5 DUMMY6 DUMMY7 DUMMY8 DUMMY9 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COMMK2 DUMMY10 DUMMY11 DUMMY12 DUMMY13 DUMMY14 DUMMY15 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 743 798 908 963 1073 1183 1293 1403 1513 1623 1733 1843 1953 2063 2173 2228 2283 2338 2393 2516 2516 2516 2516 2516 2516 2516 2516 2516 2516 2516 2516 2516 2516 2516 2338 2283 2228 2173 2118 2063 2008 1953 1898 1843 1788 1733 1678 1623 1568 1513 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -891 -142 -87 -32 23 78 133 188 243 298 353 408 463 518 573 628 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891
-6-
Ver.2004-08-06
NJU6636
! PAD COORDINATES 2
PAD No.
101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Terminal
SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18
X= m
1458 1403 1348 1293 1238 1183 1128 1073 1018 963 908 853 798 743 688 633 578 523 468 413 358 303 248 193 138 83 28 -28 -83 -138 -193 -248 -303 -358 -413 -468 -523 -578 -633 -688 -743 -798 -853 -908 -963 -1018 -1073 -1128 -1183 -1238
Y= m
891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891
PAD No.
151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Terminal
SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 DUMMY16 DUMMY17 DUMMY18 DUMMY19 DUMMY20 DUMMY21 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMMK1 DUMMY22 DUMMY23 DUMMY24
X= m
-1293 -1348 -1403 -1458 -1513 -1568 -1623 -1678 -1733 -1788 -1843 -1898 -1953 -2008 -2063 -2118 -2173 -2228 -2283 -2338 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516 -2516
Y= m
891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 891 628 573 518 463 408 353 298 243 188 133 78 23 -32 -87 -142
Ver.2004-08-06
-7-
NJU6636
! BLOCK DIAGRAM
OSC1 DNC
CR OSC
8
P/S RS R/W E/SCL DB7/CS DB6/SI DB0-DB5
Instructi on Reg. (IR)
8
Instruction Decoder ( ID )
7
Address Counter 7 7
Timing Gen.
7 I/O Buffer Data Reg. ( DR )
7
Display Data RAM ( DDRAM ) 32 x 8 bits 8 5 5 5
Character Generator RAM ( CGRAM ) 64 x 5 bits
Common Driver Segment Driver
17bit Shift Reg.
17
18 COM1COM16/ COMMK1/2
8
8 8
Character Generator ROM ( CG ROM ) 9,600 bits
SEL1 SEL2 VDD V0
Busy Flag
V0 Voltage Conv. V1
80bit Latch
Icon Display RAM ( MKRAM ) 16 x 5 bits
Cursor Blink Cont.
80
80 SEG1SEG80
5
5
Parallel to Serial Converter
5
80bit Shift Reg.
VOUT
V2 V3 V2 V3 V4 VSS V5
Reset Circuit
C1 C1 VREG VCI REGON RESETb
+
-
-8-
Ver.2004-08-06
NJU6636
! TERMINAL DESCRIPTION
PAD No 35-38 15-18 28-31 39-42 45,49 53 47,51 4-5 6-7 8-10 43 44 52 55 SYMBOL VDD, VSS I/O - FUNCTION Power Source : VDD = 2.4 to 5.5V, GND : VSS = 0V
VDDA, VSSA V0, V2, V3 OSC1 DNC P/S RS
-
-
These terminals are internally connected to the VDD and VSS level. These terminals are used to fix the selection terminals to the VDD and VSS level. VSSA should be open if not using. Note) Do not use this terminal for a main power supply. LCD Driving Voltage
I - I I
56
R/W
I
57
E SCL DB7
I I I/O
System clock input terminal This terminal should be open for internal clock operation. DNC terminal This terminal should be open. Parallel or serial interface selection terminal "L" : Serial interface / "H" : Parallel interface Resister selection signal Input "0":Instruction Resister (Writing) Busy Flag (Reading) "1":Data Register (Writing / Reading) Read/Write selection signal Input "0":Write "1":Read In serial interface mode, only data writing is available. And at the same time, R/W pin shall be fixed at VSS. Read/write activation Signal Input in parallel mode Shift clock input in serial mode 3-state Data Bus for Upper bit to transfer the data between MPU and NJU6636 in Parallel operation mode. DB7 is also Interface, "1" : Parallel Interface Chip select signal input Serial operation mode 3-state Data Bus for Upper bit to transfer the data between MPU and NJU6636 in Parallel operation mode. Data input terminal in Serial operation mode 3-state Data Bus for Lower 6bit to transfer the data between MPU and NJU6636 in Parallel operation mode. When the serial operation mode, these terminal should be open. Common driver location order select terminal Segment driver location order select terminal LCD Common driving signal output terminals Icon Common driving signal output terminals LCD Segment driving signal output terminals
58 CS DB6 59 60-65 SIO DB5- DB0 I I/O I I
48 SEL1 50 SEL2 73-80 COM1 - COM16 174-181 81, 182 COMMK1,2 88-167 SEG1 - SEG80
I I O O O
Ver.2004-08-06
-9-
NJU6636
PAD No 22-24 25-17 11-14 46 19-21
SYMBOL + C1 , C1 VCI REGON VREG
I/O I/O I I O
FUNCTION Capacitor for Voltage Converter Connecting terminal Voltage regulator input terminal Voltage regulator select terminal. REGON = "H" (Voltage regulator ON) / "0" (Voltage regulator OFF) Voltage regulator output Terminal This terminal internally connected Voltage Converter input terminal. Decupling capacitor should be connected between VREG and VSS. (C=1F) Voltage Converter Output Terminal Reset Terminal When the "L" level input over than 1.5ms to this terminal, the system will be reset. Dummy Terminal These terminal are electrically open.
32-34 54
VOUT RESETb
O I
1-3 66-72 82-87 168-173 183-185
DUMMY0-24
-
- 10 -
Ver.2004-08-06
NJU6636
! FUNCTIONAL DESCRIPTION
(1) Description for each blocks (1-1) Register The NJU6636 incorporates two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register (IR) stores Instruction codes such as "Clear Display" and "Return Home", and address data for Display Data RAM (DD RAM) and Character Generator RAM (CG RAM). The MPU can write the Instruction code and address data to the Register (IR), but it can not read out from the Register (IR). The Register (DR) is a temporary storing register, the data in the Register (DR) is written into the DD RAM or CG RAM and read out from the DD RAM or CG RAM. The data in the Register (DR) written by the MPU is transferred from the Register automatically to the DD RAM or CG RAM by Internal operation. After reading the data in the Register (DR) by the MPU, the next address data in the DD RAM or CG RAM is transferred automatically to the Register (DR) for the next MPU reading. These two registers are selected by the selection signal RS as shown below: Table 1. Register operation control by RS and R/W signals. Table 1. Register Operation RS R/W Operation 0 0 Write 0 1 Read busy flag (DB7) and address counter (DB0 to DB6)* 1 0 Write (DR to DD RAM, CG RAM or MK RAM) 1 1 Read (DD RAM, CG RAM or MK RAM to DR)* * Using Parallel Interface (1-2) Busy Flag (BF) When the internal circuits are operating, the busy flag is "1", and any instruction reading is inhibited. The busy flag (BF) is output from DB7 when RS="0" and R/W="1" as shown in table 1. The next instruction should be written after busy flag (BF) goes to "0". ( Using Parallel Interface ) (1-3) Address Counter(AC) The address Counter (AC) addresses the DD RAM and CG RAM. When the address setting instruction is written into the Register (IR), the address information is transferred from Register (IR) to the counter (AC). The selection of either the DD RAM or CG RAM is also determined by this instruction. After writing (or reading) the display data to (or from) the DD RAM or CG RAM, the counter (AC) increments (or decrements) "1" automatically. The address data in the Counter (AC) is output from DB6 to DB0 when RS="0" and R/W="1" as shown in table 1. ( Using Parallel Interface ) (1-4) Display Data RAM (DD RAM) The display data RAM (DD RAM) consisting of 32 x 8 bits stores up to 32-character display data represented in 8-bit code. The DD RAM address data set in the address Counter (AC) is represented in hexadecimal. Higher order bit AC6 AC5 AC4 Hexadecimal Lower order bit AC2 AC1 AC0 Hexadecimal (Example) DD RAM address " 08 " 0 0 0 1 0 0 0 0 8
AC
AC3
Ver.2004-08-06
- 11 -
NJU6636
The relation between DD RAM * 16 character / 2 line Display 1 2 3 4 5 st 1 line 00 01 02 03 04 2nd line 10 11 12 13 14 address and display position on the LCD is shown below. 6 05 15 7 06 16 8 07 17 9 08 18 10 09 19 11 0A 1A 12 0B 1B 13 14 0C 0D 1C 1D 15 0E 1E 16 0F 1F Display Position DD RAM Address (Hexadecimal)
The relation between DD RAM address and display position on the LCD shown below. [ Left Shift Display ] (00) 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 (10) 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 00 [ Right Sift Display ] 1F 00 01 02 03 0F 10 11 12 13
04 14
05 15
06 16
07 17
08 18
09 19
0A 1A
0B 1B
0C 1C
0D 1D
0E 1E
(0F) (1F)
- 12 -
Ver.2004-08-06
NJU6636
(1-5) Character Generator ROM(CG ROM) The Character Generator ROM (CG ROM) generates 5 x 8 dots character pattern represented in 8-bit character codes. The storage capacity is up to 240 kinds of 5 x 8 dots character pattern. The correspondence between character code and standard character pattern is shown in Table 2. User-defined character pattern ( Custom Font ) are also available by mask option. Table 2. CG ROM Character Pattern ( ROM version -02 ) Upper 4 bit (Hexadecimal)
(05)
(06)
Lower 4 bit (Hexadecimal)
(07)
(08)
Ver.2004-08-06
- 13 -
NJU6636
(1-6) Character Generator RAM The character generator RAM (CG RAM) stores any kinds of character pattern in 5 x 8 dots written by the user program to display user's original character pattern. The CG RAM stores 4 kinds of character in 5 x 8 dots mode. To display user's original character pattern stored in the CG RAM, the address data (00)H - (07)H should be written to the DD RAM as shown in Table 3. Table 3. shows the correspondence among the character pattern, CG RAM address and data. Table 3. Correspondence of CG RAM address, DD RAM character code and CG RAM character pattern (5 x 8 dots) Character Character Code CG RAM Address Pattern (DD RAM Data) (CG RAM Data) 43210 76543210 6543 210 Upper Lower Upper bit Lower bit Upper bit Lower bit bit bit 11110 000 10001 001 10001 Character 010 Pattern 11110 1000 011 0000000 Example (1) 10100 100 10010 101 110 10001 111 00000 Cursor Position 10001 000 01010 001 11111 Character 010 Pattern 00100 1001 011 0000001 Example (2) 11111 100 00100 101 110 00100 111 00000 Cursor Position 000 001 ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! ! 1111 000011 100 101 110 111 Notes: 1. Character code bits 0 to 2 correspond to the CG RAM address 3 to 5 ( 3bits : 8 patterns). 2. CG RAM address 0, 1 and 2 designate a character pattern line position. The 8th line is the cursor position and the display is performed by logical OR with cursor. Therefore, in case of the cursor display, the data of 8th line should be "0". If there is "1" in the 8th line, the bit "1" is always displayed on the cursor position regardless of cursor existence. 3. Character pattern row position corresponding to the CG RAM data bits 0 to 4 are all shown above. The bits 5 to 7 of the CG RAM do not exist. 4. CG RAM character patterns are selected when character code bits 4 to 7 are all "0" and addressed by character code bits 0 and 1. 5. "1" for CG RAM data corresponds to display On and "0" to display Off. 6. After power ON or hardware reset, the contents of CG RAM can not be initialized, be sure to set the RAM before display ON.
- 14 -
Ver.2004-08-06
NJU6636
(1-7) Icon Display RAM (MK RAM) The NJU6636 can display maximum 80 Icons. The Icon Display can be controlled by writing the data in MK RAM corresponds to the Icon. The relation between MK RAM address and Icon Display position is shown in Table 4. COMMK1 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COMMK2 123 Table 4. Correspondence among Icon Position, MK RAM Address Data Bits for Icon Display Position MK RAM Address (20H to 2FH) D7 D6 D5 D4 D3 D2 0010 0000 20H * * * 1 2 3 0010 0001 21H * * * 6 7 8 0010 0010 22H * * * 11 12 13 0010 0011 23H * * * 16 17 18 0010 0100 24H * * * 21 22 23 0010 1100 0010 1101 0010 1110 0010 1111
Notes:
*** *** *** *** *** *** *** *** *** ***
78 79 80
D1 4 9 14 19 24 63 68 73 79
D0 5 10 15 20 25 64 69 74 80
2CH 2DH 2EH 2FH
* * * *
* * * *
* * * *
60 65 70 75
61 66 71 76
62 67 72 78
1. When the Icon display function using, the system should be initialized by the software initialization because of the MK RAM does not initialize except the software initialization 2. In the table 4, the bits D5 to D7 mentioned by * are invalid.
Ver.2004-08-06
- 15 -
NJU6636
(1-8) Timing Generator The timing generator generates a timing signals for the DD RAM, MK RAM, CG RAM, CG ROM and other internal circuit operation. RAM read timing for the display and internal operation timing for MPU access are separately generated, so that they may not interfere with each other. Therefore, when the data write to the DD RAM for example, there will be undesirable Influence, such as flickering, in areas other than the display area. (1-9) LCD Driver LCD driver consists of 18-common driver and 80-segment driver. 80 bits of character pattern data are shifted in the shift-register and latched when the 80 bits shift performed completely. This latched data controls display driver to output LCD driving waveform. (1-10) Cursor Blinking Control Circuit This circuits controls cursor On/Off and cursor position character blinks. position at the DD RAM address set in the address counter(AC). When the address counter is (04)H, a cursor position is shown as follows: AC6 0 3 02 12 4 03 13 AC5 0 5 04 14 AC4 0 6 05 15 AC3 0 AC2 1 AC1 0 11 0A 1A AC0 0 12 0B 1B 13 14 0C 0D 1C 1D 15 0E 1E 16 0F 1F Display Position DD RAM Address (Hexadecimal)
The cursor or blinks appears in the digit
AC 1 00 10 2 01 11
1st line 2nd line
7 8 9 10 06 07 08 09 16 17 18 19 Cursor Position
Note)
The cursor or blinks appears when the address counter (AC) selects the CG RAM. But the displayed cursor and blink are meaningless. If the AC stores the CG RAM address data, the cursor and blink are displayed in the meaningless position.
- 16 -
Ver.2004-08-06
NJU6636
(2) Power on Initialization by internal circuits (2-1) Initialization By internal Reset circuits The NJU6636 is initialized automatically by the internal power on initialization circuits when the power is turned on. In the internal power on initialization, following instructions are executed. During the internal power on initialization, the busy flag (BF) is "1" and this status is kept 10ms after VDD = 2.4V. Initialization flow is shown below: Clear Display Function Set Power Control N=1 :16-character 2-Line PD,2=0 :Power Down OFF V=0 :Voltage Converter OFF Setting RE register "000". D=0 C=0 B=0 I/D=1 S=0 :Display Off :Cursor Off :Cursor Blink Off :Increment by 1 :No Shift
Display On/Off Control
Entry Mode Set
Note) If the condition of power supply rise time described in the Electrical Characteristics is not satisfied, the internal Power on initialization Circuits will not operate and initialization will not be performed. In this case, the initialization by MPU software is required.
(2-2) Initialization By Hardware The NJU6636 incorporates RESET terminal to initialize the all system. When the "L" level input over than 1.5ms to the RESET terminal, the reset sequence is executed. In this time, the busy signal output during 10ms after RESET terminal goes to "H".
*
Operation timing External Reset Signal Counter Output RS-F/F Output Internal Reset Signal BUSY
Over 1.5ms
10ms
Ver.2004-08-06
- 17 -
NJU6636
(3) Instructions The NJU6636 incorporates two resisters, which are Instruction Register (IR) and a Data Register (DR). These two registers store control information temporarily to allow interface between NJU6636 and MPU or peripheral ICs operating different cycles. The operation of NJU6636 is determined by this control signal from MPU. The control information includes register selection signals (RS), read/write signals (R/W) and data bus signals (DB0 to DB7). Table 5. Shows each instruction and its operating time. Table 5. Table of Instruction
INSTRUCTION Maker Test Clear Display Return Home / Font Size Set CODE
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
All "0" code is using for maker testing. Display clear and sets DD RAM address 0 in AC. Sets DD RAM address 0 In AC and returns display being shifted to original position. DD RAM contents remain unchanged. Sets cursor move direction and species shift of display are performed In data read/write. I/D=1:Increment, I/D=D:Decrement,S=1:Accopa nies display shift. Sets of display On/Off(D), cursor On/Off(C) and blink of cursor position character(B) Move cursor and shifts display without changing DD RAM contents. S/C=1 : Display shift S/C=0 : Cursor shift R/L=1 : Shift to right R/L=0 : Shift to the left Sets number of display lines (N) and power down mode (PD2, PD). N=0 : 16-Character 1-Line N=1 : 16-Character 2-Line PD2=0 : Power down 2 OFF PD2=1 : Power down 2 ON PD=0 : Power down OFF PD=1 : Power down ON Sets Voltage Doubler ON/OFF. (V), sets data to Voltage regulator. Sets RAM address. After this instruction, the data is transferred to / from RAM. Read busy flag and AC contents (Note2) BF=1 : Internally operating BF=0 : Can accept instruction Writes data into CG, MK or DD RAM. Reads data from CG, MK or DD RAM (Note2)
EXEC TIME (fOSC=110kHz)
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 0
0 0 1
0 1 *
- 1500s 91s
Entry Mode Set
0
0
0
0
0
0
0
1
I/D S
91s
Display ON/OFF Control Cursor or Display Shift
0
0
0
0
0
0
1
D
C
B
91s
0
0
0
0
0
1 S/C R/L
136.4s
Function Set
0
0
0
0
1
1
N
0
PD2 PD
91s
Power Control Set RAM Address Read Busy Flag & Address
0 0 0
0 0 1
0 1 BF
1
0
V
0
RE
91s*1 91s 0s
RAM address AC Write Data(DD RAM)
Write Data to CG, MK or DD or MK 1 RAM Read Data from CG, MK or DD RAM 1 Explanation of Abbreviation
0

91s
(CG, MK RAM) 136.4s
1
Read Data(DD RAM) (CG, MK RAM)
DD RAM : Display data RAM, CG RAM : Character generator RAM ACG : CG RAM address, ADD : DD RAM address, Corresponds to cursor address AC : Address counter used for both DD and CG RAM
=Don't Care Note1: fOSC=110kHz when the fOSC changes, the execute time also changes. Execution time of the Power control instruction is the internal that from the instruction executed by internal circuit to the instruction sent to the power supply circuit. In actual application the power supply system need longer time to stabilize. Note2: Using Parallel Interface only.
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Ver.2004-08-06
NJU6636
(3-1) Description of instruction (a) Maker Test Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0
All "0" code in 8-bit length is usable for NOP ( Not Operating instruction ). (b) Clear Display Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1
Clear display instruction is executed when the code "1" is written into DB0. In case of normal display mode, when this instruction is executed, the space code (20)H is written into every DD RAM address, the DD RAM address 0 is set into the address counter and entry mode is set an increment. If the cursor or blink are displayed, they are returned to the left end of the LCD. The S of entry mode and CG RAM data does not change. In case of double height mode, when this instruction is executed, the space code (20)H is written into DD RAM address,(00)H to (0F)H. Note: The character pattern for character code (20)H must be blank code in the user-defined character pattern( Custom font ). (c) Return Home / Font Size Set Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 1 DB0 *
Return home instruction is executed when the code "1" is written Into DB1. When this Instruction is executed, the DD RAM address 0 is set to address counter. Display is returned to the original position if shifted, the cursor or blink is returned to the left end of the LCD. If the cursor or blink are on the display, the DD RAM contents are not changed. (d) Entry Mode Set Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 0 DB2 1 DB1 I/D DB0 S
Entry mode set instruction which sets cursor moving direction and display shift On/Off, is executed when the code "1" is written into DB2 and the codes of (I/D) and (S) are written into DB1 (I/D) and DB0 (S) as shown below. (I/D) sets the address increment or decrement, and the (S) sets the entire display shift in the DD RAM writing. I/D 0 1 FUNCTION Address increment : The address of the DD RAM increment ( +1) when the read/write, and the cursor or blink moves to the right. Address decrement : The address of the DD or CG RAM decrement ( -1) when the read/write, and the cursor or blink move to the left. FUNCTION Entire display shift. The shift direction is determined by I/D: shift to the left at I/D=1 and shift to the right at the I/D=0. The shift is operated with only the character, so that it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DD RAM and writing/reading into/from CG RAM. The display does not shifting
S 1
0
Ver.2004-08-06
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NJU6636
(e) Display ON/OFF Control Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 0 DB3 1 DB2 D DB1 C DB0 B
Display On/Off control instruction which controls the display On/Off, the cursor On/Off and the cursor position character blink, is executed when the code "1" is written into DB3 and the codes of (D), (C) and (B) are written into DB2(D), DB1(C) and DB0(B) as shown below. D 1 0 FUNCTION Display On. Display Off. In this mode, the display data remains in the DD RAM so that it is retrieved immediately on the display when the D change to 1. FUNCTION Cursor On. The cursor is displayed by 5 dots on the 8th line. Cursor Off. Even if the display data write, the I/D etc does not change. FUNCTION The cursor position character is blinking. Blinking rate is 395.6ms (2-line) and 418.9ms (1-line) at fOSC=110kHz. The blink is displayed alternatively with all on (it means all black) and characters display. The cursor and the blink can be displayed simultaneously. The character does not blink.
C 1 0 B 1
0
!"""! "!!!" "!!!" "!!!" """"" "!!!" "!!!" """""
!"""! "!!!" "!!!" "!!!" """"" "!!!" "!!!" !!!!!
""""" """"" """"" """"" """"" """"" """"" """""
Character Font 5 x 7dots (1) Cursor display example
Alternating display (2) Blink display example
The cursor or blinks also appear when the address counter (AC) selects the CG RAM. But the displayed cursor and blink are meaningless. If the AC storing the CG RAM address data, the cursor and blink are displayed in the meaningless position.
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Ver.2004-08-06
NJU6636
(f) Cursor Display Shift Code RS 0 R/W 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 S/C DB2 R/L DB1 DB0 =Don't Care
The Cursor/Display shift instruction shifts the cursor position or display the right or left without writing reading display data. The contents of address counter (AC) is not changed by operation of display shift only. This instruction is executed when the code "1" is written into DB4 and the codes of (S/C) and (R/L) are written into DB3 (S/C) and DB2(R/L) as shown below. S/C 0 0 1 1 R/L 0 1 0 1 FUNCTION Shifts the cursor position to the left ((AC) is decrement by 1) Shifts the cursor position to the right ((AC) is incremented by 1) Shifts the entire display to the left and the cursor follows it. Shifts the entire display to the right and the cursor follows it.
(g) Function Set Code RS 0 R/W 0 DB7 0 DB6 0 DB5 1 DB4 1 DB3 N DB2 0 DB1 PD2 DB0 PD =Don't Care
Function set instruction which sets the number of display lines and power down mode, is executed when the code "1" is written into DB5, DB4 and the codes of (N), (PD2) and (PD) are written into DB3 (N), DB1 (PD2), and DB0 (PD) as shown below (character font is fixed 5 x 8 dots). Note) This function set instruction must be performed at the head of the program prior to all other instructions (except Busy flag/Address read). N 0 1 PD2 0 1 PD 0 1 FUNCTION Set the 16-Character 1-Line Display Set the 16-Character 2-Line Display FUNCTION Normal operation Power down mode on ( The display goes to off automatically ) FUNCTION Normal operation Power down mode on ( The display goes to off automatically )
Ver.2004-08-06
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NJU6636
(h) Set Power Control RS 0 R/W 0 DB7 DB6 DB5 DB4 0 1 0 V Higher order bit DB3 DB2 DB1 DB0 C1 C0 0 C2 Lower order bit
Code
Power Control instruction which sets the Voltage Doubler, Oscillator ON/OFF and sets data to Voltage Regulator, is executed when the code "1" is written into DB6 and the codes of (V) and (C2 to C0) are written into DB4 (V) and DB2 to DB0 (C2 to C0), as shown below. V 0 1 FUNCTION Voltage Converter stop the operation Voltage Converter starts the operation
C2 0 0 0 0 1 1 1 1
C1 0 0 1 1 0 0 1 1
C0 0 1 0 1 0 1 0 1
VREG(V) Min.
Max.
(i) Set RAM Address Code RS 0 R/W 0 DB7 DB6 DB5 DB4 1 A A A Higher order bit DB3 DB2 DB1 DB0 A A A A Lower order bit
Set CG RAM address instruction is executed when the code "1" is written into DB7 and the address is written into DB6 to DB0 as shown above. The address data (DB6 to DB0) is written into the address counter (AC) by this instruction. Affter this instruction execution, the data writing / reading is performed into / from the address RAM. The RAM includes DD RAM, CG RAM and MK RAM are shared by address as shown below.
st
DD RAM DD RAM MK RAM CG RAM
1 Line : nd 2 Line : 80icon : 8character :
CG RAM address from (00)H to (0F)H from (10)H to (1F)H from (20)H to (2F)H from (40)H to (7F)H
(j) Read Busy Flag & Address Code RS 0 R/W 1 DB7 DB6 DB5 DB4 BF A A A Higher order bit DB3 DB2 DB1 DB0 A A A A Lower order bit
This instruction reads out the internal status of the NJU6636. When this instruction is executed, the busy flag (BF) which indicates the internal operation, is read out from DB7 and the address of CG RAM, MK RAM or DD RAM is read out from DB6 to DB0 (an address for CG RAM, MK RAM or DD RAM is determined by the previous instruction). Using parallel Interface only. (BF)=1 indicates that internal operation is in progress. The next instruction is inhibited when (BF)=1. Check the (BF) status before the next write operation.
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Ver.2004-08-06
NJU6636
(k) Write Data to RAM Write data to DD RAM RS R/W Code 1 0 DB7 DB6 DB5 DB4 D D D D Higher order bit DB3 DB2 DB1 DB0 D D D D Lower order bit DB3 DB2 DB1 DB0 D D D D Lower order bit
Write data to CG RAM, MK RAM RS R/W DB7 DB6 DB5 DB4 Code 1 0 * * * D Higher order bit
=Don't Care
Write Data to CG RAM, MK RAM or DD RAM instruction is executed when the code "1" is written into (RS) and code "0" is written into (R/W). By the execution of this instruction, the binary 5-bit data "DDDDD" are written into the CG RAM or MK RAM, and the binary 8-bit data "DDDDDDDD" are written into the DD RAM. The selection of the CG RAM or DD RAM is determined by the previous instruction. After this instruction execution, the address increment(+1) or decrement(-1) is performed automatically according to the entry mode set. And the display shift is also executed according to the previous entry mode set. (l) Read Data from RAM Read data to DD RAM RS R/W Code 1 1 DB7 DB6 DB5 DB4 D D D D Higher order bit DB7 DB6 DB5 DB4 D Higher order bit DB3 DB2 DB1 DB0 D D D D Lower order bit DB3 DB2 DB1 DB0 D D D D Lower order bit
Read data to CG RAM RS R/W Code 1 1
=Don't Care
Read Data to CG RAM or DD RAM instruction is executed when the code "1" is written into (RS) and (R/W). By the execution of this instruction, the binary 5-bit data "DDDDD" are read out from CG RAM, MK RAM and the binary 8-bit data "DDDDDDDD" are read out from DD RAM. The selection of the CG RAM or DD RAM is determined by the previous instruction. (Using parallel Interface) Before executing this instruction, either the CG RAM address set or DD RAM address set must be executed, otherwise the first read out data Invalidated. When this instruction is serially executed, the next address data is normally read from the second read. The address set instruction is not required if the cursor shift instruction is executed just beforehand (only DD RAM reading). The cursor shift instruction has same function as the DD RAM address set, so that after reading the DD RAM, the address increment or decrement is executed automatically according to the entry mode. But display shift does not occur regardless of the entry mode. Note) The address counter (AC) is automatically incremented by 1 after write instructions to either of the CG RAM, MK RAM or DD RAM. Even if the read instruction is executed after this instruction, the addressed data can not be read out correctly. For a correct data read out, either the address set instruction or cursor shift instruction (only with DD RAM) must be implemented just before this instruction or from the second time read out instruction execution if the read out instruction is executed 2 times consecutively.
Ver.2004-08-06
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NJU6636
(3-2) Initialization by instruction If the power supply conditions for the correct operation of the internal reset circuits are not method, the NJU6636 must be initialized by the instruction. Note Power On Wait more than 10 ms after VDD rises to 2.4V RS 0 RS 0 RS 0 RS 0 RS 0 Using parallel Interface. After this step, busy flag (BF) check or longer waiting time than each instruction execution time is required R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Voltage Doubler : ON 0 0 1 0 1 0 0 0 0 VREG setting : "000" R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Set the 2-line Display, 0 0 0 1 1 1 0 0 0 Power Down "OFF" R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 0 0 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 1 Example for set address R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 increment and cursor right 0 0 0 0 0 0 1 1 0 shift when the data write to the DD, CG or MK RAM.
Power Control
Function Set
Display OFF
Display Clear
Entry Mode Set
Write data to the CG, MK or DD RAM And set the instruction.
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Ver.2004-08-06
NJU6636
(4) Power Down function NJU6636 incorporates two power down mode to decrease the operating current during standby status. The status of internal circuits at the two power down mode is shown below : PD ="1": Voltage converter, Voltage regulator and Oscillator stops operation. Segment and Common drivers output VSS level. The contents of DD RAM, CG RAM and MK RAM are saved. PD2="1": Voltage converter and Voltage regulator stops operation. Segment and Common drivers output VSS level. The contents of DD RAM, CG RAM and MK RAM are saved. Note. The other instruction one unavailable after Power Down functioned. Make sure to turn off Power Down function before executing other instructions. Executing the Display OFF before Power Down is recommended. If Power Down is executed during Display ON, unexpected pixels may be turned on. (5) LCD DISPLAY (5-1) LCD Powr supply NJU6636 incorporates a 2 x Voltage Converted and bleeder resistance to generate the waveform of LCD driving high voltage. (a) Voltage converter By connecting the capacitor between C1+ and C1-, VSS and VOUT respectively, VCI or VREG ( set by internal voltage regulator ) is 2 times boosted and output from VOUT. VOUT=2 x VREG VREG
VSS= 0V (b) Voltage regulator Voltage regulator generates the reference voltage to Voltage Converter by setting the VREG ON terminal. VREGON = "1" :Voltage regulator ON VREGON = "0" :Voltage regulator OFF VCI VREGON VREGON="1" REGON="0" Voltage Converter VREG C1+ C1VREG VOUT
VSS
Recommend value : C=1F
Note) Recovery from Power Down status or just after power ON, it need 10mS for LCD Power Supply circuit to function, please set waiting time till display ON.
Ver.2004-08-06
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NJU6636
(c) Bleedr Resistance Each LCD driving voltage (V1, V2, V3, V4 ) is generated by the bleedr resistance. The bleeder resistance is set 1/5 bias suitable for 1/17 duty ration and 40k(Typ.) resistance total. LCD Driving Voltage vs. Duty Ratio Duty Ratio 1/17, 1/9 Bias 1/5 V2 3/5V0 V3 2/5V0 VSS VSS
Power Supply
The VLCD is maximum swing of LCD waveform.
NJU6636 V0 R k V1
R k V2 V2 R k V3 R k V3 VLCD
V4
R k VSS
V5
LCD Driving Voltage example
Note) Power ON or power OFF is in the following order. 1. Using the internal power Supply Power ON : First VDD, then VCI power ON, after the built-in Voltage Regulator outputting stabilized VREG, turn the Voltage Converter on. After the Voltage Converter stabilized, Execute Display ON instruction Power OFF: First Display OFF, then stop the operation of the Voltage Converter, turn off the VCI and then turn off the VDD. 2. Using the external Power Supply Power ON : V0 should be turned on after the VDD turned on. Power OFF : After Display OFF, turn off the V0 and then turn off the VDD.
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Ver.2004-08-06
NJU6636
(d) Internal power supply operation (1/5 Bias) Voltage Converter, Voltage Reglator Using Voltage Converter Using
VCI=VDD=3V
VCI=VDD=3V
VDD VCI VREG VOUT V0 VSS + C1 C1
-
V2 V3
VDD Open VDD VCI VREG VOUT V0 VSS + C1 C1
-
V2 V3
Open
NJU6636
REGON
NJU6636
REGON
(e) External power supply operation (1/5 Bias)
V0=5V VDD=3V
VDD VCI VREG VOUT V0 VSS + C1 Open C1
-
V2 V3
Open
NJU6636
REGON
Ver.2004-08-06
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NJU6636
(f) Internal power supply operation (1/4 Bias) Voltage Converter, Voltage Reglator Using Voltage Converter Using
VCI=VDD=3V
VCI=VDD=3V
VDD VCI VREG VOUT V0 VSS + C1 C1
-
V2 V3
VDD VCI VREG VDD VOUT V0 VSS + C1 C1
-
V2 V3
NJU6636
REGON
NJU6636
REGON
(g) External power supply operation (1/4 Bias)
V0=5V VDD=3V
VDD VCI VREG VOUT V0 VSS + C1 Open C1
-
V2 V3
NJU6636
REGON
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Ver.2004-08-06
NJU6636
(6) Relation between oscillation frequency and LCD frame frequency. LCD frame frequency example mentioned below is based on 110kHz oscillation. (1 clock = 9.091s)
*
1/17 duty Clock 1 V0 V1 V2 V4 VSS 1 frame 1 frame 2 3 4 ****** 17 1 2 3 4 ****** 17 1 2 3
1 frame = 9.091(s) x 80 x 17 = 12.36(ms) Frame frequency = 1/12.36(ms) = 80.88(Hz)
*
1/9 Duty Clock 1 VLCD V1 V2 V4 VSS 1 frame 1 frame 2 3 4 ****** 9 1 2 3 4 ****** 9 1 2 3
1 frame = 9.091(s) x 80 x 9 = 6.55(ms) Frame frequency = 1/6.55(ms) = 152.78(Hz) (7) Interface with MPU Interface circuits of NJU6636 can be connected to serial or 8-bit parallel. (7-1) 8-bit MPU interface RS R/W E Internal Status DB7
Data
Operation
Busy Busy No Busy Data
Instruction Writing
Busy Flag Check
Busy Flag Check
Busy Flag Check
Instruction Writing
Ver.2004-08-06
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NJU6636
(7-2) Serial Interface with MPU Serial interface circuit is activated when the P/S terminal is set to "L" level (VSS) then the chip select terminal(CS) goes to "L" level. The data input is MSB first like as the order of DB7, DB6 to DB0. The input data is entered into the shift register synchronized at the rise edge of the serial clock SCL. The shift register converted to parallel data at the CS rise edge input. In case of entering over than 8-bit data, valid data is last 8-bit data. The output data is exited from the shift register synchronized at the fall edge of the serial clock SCL. The time chart for the serial interface is shown below. Furthermore, in serial interface mode, only data writing is available. And at the same time, R/W pin shall be fixed at VSS. P/S RS R/W CS SCL SI DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Note : The level ("L" or "H") of RS terminal should be set before CS terminal goes to "L" level.
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Ver.2004-08-06
NJU6636
! ABSOLUTE MAXIMUM RATINGS
PARAM ET ER Supply Voltage Input Voltage Operating Temperature Storage Temperature SYMBOL VDD VIN Topr Tstg
(Ta=25C)
RAT I N G S -0.3 to +7.0 -0.3 to VDD+0.3 -40 to +85 -55 to +125 UNIT V V C C
Note 1.) If the LSI is used on condition above the absolute maximum ratings, the LSI may be destroyed. Using the LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the electric characteristics conditions will cause malfunction and poor reliability. Note 2.) Decoupling capacitor should be connected between VDD, Vci,, V0 and VSS. Note 3.) All voltage values are specified as VSS =0V Note 4.) The relation VDD>VSS, Vci>VSS VSS=0V must be maintained. V0 should be turned on after the VDD turned on.
! ELECTRICAL CHARACTERISTICS ( Applies to NJU6636A )
SYMBOL VDD VIH1 Input Voltage 1 VIL1 IOH Output Voltage IOL RCOM Driver On-resist. (COM/SEG) RSEG Input Leakage ILI Current Pull-up Resist -IP Current IDD ICI Operating IREG Current IO ISTB1 ISTB2 LCD Driving VLCD Voltage Bleeder Resist. Oscillation Freq. Ext. CLK Freq. Ext. CLK Duty RB fOSC fCP Duty PARAMETER Operating Volt. SYMBOL VDD
(VDD=2.4 to 5.5V, VSS=0V, Ta=-40 to 85C)
MIN 2.4 0.8VDD -IOH=0.205mA 2 IOL=1.6mA, VDD=3V - Id=1A , V0=3/6V (All com. Term.) - Id=1A , V0=3/6V (All Seg. Term.) - VIN=0 to VDD
VDD=3V, VIN=0V (ALL DB Term.)
TYP - - - - - - 11 60 240 4 125 3 25 - 40 110 110 50 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 0.2 - - 5.8
MAX UNIT 5.5 V VDD V 0.2VDD V - V 0.5 V 20 k 30 k 1 50 200 30 400 10 100 6.0 46 130 130 55 2.266 2.369 2.472 2.575 2.678 2.781 2.884 2.987 0.6 6 200 - A A A A A A A A V k kHz kHz %
NOTE 5 6 7 7 9
-1 - - - - - - - 3.0 34 90 90 45 2.134 2.231 2.328 2.425 2.522 2.619 2.716 2.813 - 3.5 - 5.4
VDD=3V, Display ON fOSC=110kHz (CR Oscillation) Internal Regulator ON : "000" VIN=0V or 3V Ta=25C
VDD=VCI=3V, PD=1, Ta=25C VDD=VCI=3V, PD2=1, Ta=25C V0 Terminal, VDD=3V VDD-VSS=5V, RB=(V0-VS)/IB, Ta=25C
10
Output Volt.
VREG
VIN-VOUT Input Volt. Lord Reg. Output Voltage
VIO VCI VREG VOUT
VDD=3V, Ta=25C OSC1 Terminal OSC1 Terminal REG : ( 000 ) REG : ( 001 ) REG : ( 010 ) VCI=5V, REG : ( 011 ) Ta=25C REG : ( 100 ) REG : ( 101 ) REG : ( 110 ) REG : ( 111 ) IOUT=1mA, Ta=25C Regulator Using VCI=5V, IOUT=1-5mA, Ta=25C VCI=3V, REGON, Ta=25C
Int. Regulator
V
11
V V mV V
11 11 11 12
Ver.2004-08-06
- 31 -
NJU6636
* *
Input / Output structure except LCD driver are shown below: Input Terminal Structure E, RESb Terminals
OSC1Terminal VDD Internal Circuit PMOS PMOS
NMOS VSS
NMOS VSS
*
Input / Output Terminal Structure DB0 to DB7 Terminals VDD VDD PMOS PMOS VDD NMOS VSS PMOS ENABLE DATA
NMOS VSS
Note 5.) OSC1, P/S, RS, R/W, E, SCL, DB7 to DB0, SEL1, SEL2, REGON, RESb Note 6.) DB7 ( CS) , DB6 ( SIO ), DB5 to DB0. Note 7.) RCOM and RSEG are the resistance values between power supply terminals ( V0, V2, V3, Vss ) and each common terminal (COM1 to COM16), and supply voltage (V0, V2, V3, Vss) and each segment terminal ( SEG1 to SEG80 ) respectively, and measured when the current Id is flown on every common and segment terminals at the same time. Note 8.) P/S, RS, R/W, E, SCL, SEL1, SEL2, REGON, RESb. Note 9.) DB7(CS), DB6(SIO), DB5 to DB0. Note 10.) IDD : Applies to the VDD. - VOUT and V0 are connected, Voltage Converter ON ICI : Applies to the VCI. - VOUT and V0 are connected, Voltage Converter ON IREG: Applies to the VCI. - VOUT is open, V0=5V, Voltage Converter OFF I0: Applies to the V0. - VOUT is open, V0=5V, voltage Converter OFF ISTB1: Applies to the VDD and VCI. - VOUT and V0 are connected. ISTB2: Applies to the VDD and VCI . - VOUT and V0 are connected. Use 1F capacitor connecting VREG - VSS, C1- - C1+, VOUT - VSS, and evaluate via VREG. Note 11.) VREG - Use 1F capacitor connecting VCI - VSS, VREG - VSS, and evaluate via VREG. Note 12.) VOUT - Connect VOUT and V0, and use 1F capacitor connecting VREG - VSS, C1- - C1+ and VOUT - VSS.
- 32 -
Ver.2004-08-06
NJU6636
! Bus timing characteristics
*
(VDD=2.4 to 5.5V, VSS=0V, Ta=-40 to 85C)
MAX UNIT CONDITION - - 20 ns Fig.1 - - - - Lord Condition of DB0 to DB7 : CL=100pF
VIH VIL tAH VIL PWEH VIH VIH tDSW VIH Data VIL tCYCE VIL tAH tEf PWEL VIL VIH
Write operation sequence (write from MPU to NJU6636) PARAMETER SYMBOL MIN Enable Cycle Time tCYCE 1000 Enable Pulse Width "High" level PW EH 400 Enable Rise Time, Fall Time tEr, tEf - Set up Time RS, R/W-E tAS 200 Address Hold Time tAH 200 Data Set up Time tDSW 200 Data Hold Time tH 200 Timing Characteristics (Write Operation) RS
VIH VIL tAS
R/W
VIL
E
tEr
VIL
VIL tH
DB0 - DB7
*
Fig.1 Read operation sequence ( Read from NJU6636 to MPU) PARAMETER SYMBOL MIN Enable Cycle Time tCYCE 1000 Enable Pulse Time "High" level PW EH 600 Enable Rise Time, Fall Time tEr, tEf - Set up Time RS, R/W-E tAS 200 Address Hold Time tAH 200 Data Delay Time tDDR - Data Hold Time tDHR 0 Timing Characteristics (Read Operation) RS
VIH VIL tAS
MAX UNIT CONDITION - - 20 ns Fig.2 - - 600 - Lord Condition of DB0 to DB7 : CL=100pF
VIH VIL tAH VIH
R/W
VIH PWEH VIH tDDR VOH Data VOL tCYCE VIH tAH tEf
PWEL VIL VOH
E
tEr
VIL
VIL tDHR
DB0 - DB7
VOL
Fig. 2
Ver.2004-08-06
- 33 -
NJU6636
! Bus timing characteristics
*
(VDD=2.4 to 5.5V, VSS=0V, Ta=-40 to 85C)
SYMBOL tCYCE tSCH tSCL tSCR, tSCF PWCS tCSU tCH tCSR,tCSF tAS tAH tDSISU tSIH MIN 1000 300 700 - MAX - - - 20 UNIT CONDITION
Serial Interface sequence PARAMETER Serial Clock Cycle Time "High" level Serial Clock Width "Low" level Serial Clock Rise Time, Fall Time Chip Select Pulse width Chip Select Set Up Time Chip Select Hold Time Chip Select Rise Time, Fall Time Set up Time RS-E Address Hold Time Serial Input Data Set up Time Serial Input Data Hold Time Serial Interface RS
VIH VIL
ns 200 200 200 200 - - - -
Fig.3
VIH VIL
R/W
tAS tCSU VIL tCSF tSCR tSCH tSCF tSCL tCSR tCYCE tCH tAH VIH PWCS
CS
SCL
tSISU tSIH
SI
VIH VIL
Fig. 3
- 34 -
Ver.2004-08-06
NJU6636
*
The Input Condition when using the Hardware Reset Circuit PARAM ET ER SYMBOL CONDITION RESET input tRSL fOSC =110kHz "Low" level width Input timing VRSL
MIN 1.5
TYP -
(Ta=-40 to 85C) MAX UNIT - ms
RESET VIL
*
Power supply condition when using the internal initialization circuit PARAM ET ER SYMBOL CONDITION MIN Power supply rise time trDD - 0.1 Power supply OFF time tOFF - 1
TYP - -
(Ta=-40 to 85C) MAX UNIT 5 ms - ms
2.2V VD 0.2V 0.2V tOFF tOFF 1ms trDD 0.1ms trDD 5ms
3V
*tOFF specifies the power OFF time in a short period OFF or cyclical ON/OFF
Note.) Since the internal initialization circuits will not operate normally unless the above conditions are met, in such a case initialize by instruction(Refer to initialization by the instruction).
Ver.2004-08-06
- 35 -
NJU6636
! LCD DRIVING WAVE FROM
NJU6636 1/17 Duty driving
COMMK COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 V0 V1 V2 V3 V4 V5 V0 V1 V2 V3 V4 V5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
COMMK
COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COMMK SEG1 SEG2 SEG3 SEG4 SEG5
COM1
V0 V1 V2 V3 V4 V5
COM16
V0 V1 V2 V3 V4 V5 V0 V1 V2 V3 V4 V5
SEG1
SEG2
- 36 -
Ver.2004-08-06
NJU6636
! APPLICATION CIRCUITS
SEL1=0, SEL2=0
COMMK1 COM1
COM8
LCD Panel ( 16-character 2-line with Icon Display )
COM9
COM16 COMMK2 SEG1 SEG80
SEG1 COM8
SEG80 COMMK2 COM16
NJU6636 TOP VIEW
COM1 COMMK1 COM9
SEL1=1, SEL2=1
COM8 COMMK2 COM16
COM1 COMMK1 SEG1
NJU6636 TOP VIEW
COM9 SEG80
SEG1 COMMK1 COM1
SEG80
COM8
LCD Panel ( 16-character 2-line with Icon Display )
COM9
COM16 COMMK2
Ver.2004-08-06
- 37 -
NJU6636
SEL1=0, SEL2=1
COMMK1 COM1
COM9
LCD Panel ( 16-character 2-line with Icon Display )
COM8
COM16 COMMK2 SEG1 SEG80
SEG1 COMMK2 COM16
SEG80 COM8
NJU6636 BOTTOM VIEW
COM1 COMMK1
COM9
SEL1=1, SEL2=0
COMMK2 COM16 COM8
NJU6636 BOTTOM VIEW
COM9 SEG1
COM1 COMMK1 SEG80
SEG1
SEG80 COMMK1 COM1
COM9
LCD Panel ( 16-character 2-line with Icon Display )
COM8
COM16 COMMK2
- 38 -
Ver.2004-08-06
NJU6636 MEMO
[CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.
Ver.2004-08-06
- 39 -

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